very high speed FPGAs

Source

At heart of the FPGAs is a fabric of asynchronous logic. But the fabric has been designed so that its asynchronous nature is invisible to designers and to front-end synthesis tools.
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The tale starts with one of the less popular approaches to asynchronous logic: two-wire signaling with a separate acknowledge wire, also known as three-wire asynchronous logic
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Each LUT, by waiting until its inputs are ready and holding its output until its clients have acknowledged, in effect acts as a self-timed latch.
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The fabric implements a logic design by turning each logic level into a pipeline stage.
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All of the asynchronous signals are local to the logic fabric, and cannot be accessed by users. The fabric is surrounded by a fully synchronous ring of registers which—with a large helping of secret sauce—resynchronize the stuff going on inside the fabric so that at the pins, the device appears to be a fully synchronous,
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You enter your RTL, synthesize it, and map it onto familiar-looking 4-LUT logic elements. The Achronix back-end tool, in effect, pipelines all of your logic into pipes with 1-gate-delay stages, and turns the clock up accordingly. And you get a fast, apparently fully synchronous FPGA design.
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Because the heart of these FPGAs is self-timed, there are no huge clock networks running through the logic fabric. In fact there are no clocks in the logic fabric at all—they are all in the synchronization ring that surrounds the fabric. That means that the chip does not have the huge power dissipation—both dynamic and static--in clock networks that conventional FPGAs must have. And it does not exhibit the huge supply current spikes characteristic of any large synchronous design.
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Because the majority of the circuits in the chip are self-timed, you don't have all the logic transitions in a clock domain happening at the same time, on each clock edge. The transitions are smeared out over time. Looking at a trace of supply current vs. time, you simply don't see the huge current spikes aligned with clock edges that so drive FPGA designers mad worrying about decap insertion, instantaneous IR drop, signal integrity and electromigration