Low power and FPGAs

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FPGA designer has just a few knobs to turn. There’s the choice of programming element e.g. Actel, whose Flash programming cell can have considerably lower operating power than an SRAM-based cell.

Dynamic power is a different issue. “The big culprit in FPGAs is the clocks
Another important issue for FPGA dynamic power is, perhaps surprisingly, inrush current. “Battery life is non-linear in current,”
“So large current spikes reduce battery energy disproportionately. You must eliminate them.” That means not only preventing inrush current on power-up, but in all modes of the chip avoiding hazardous transition states that could result in spikes on the supply busses